#asic
Remoticon 2021 // Matt Venn Helps You Make ASICS
What would you make if you were given about ten square millimeters of space on a silicon wafer on a 130 nm process? That's the exact question that the Open MPW program asks, and that [Matt Venn] has stepped up to answer. [Matt] came to Remoticon in 2020 to talk about his journey from nothing to his own ASIC, and he came back in 2021 to talk about what has happened in a year.
[maxiborga] has been making beautiful renders of his and others' chip designsWe expected great designs, but the variety of exciting and wonderful designs that have been submitted we think exceeded our expectations. [Matt] goes through quite a few of them, such as an analog neuron, a RISC-V Arduino-compatible microprocessor, and a satellite transceiver. Perhaps an unexpected side effect has been the artwork. Since the designs are not under an NDA, anyone can take the design and transform it into something gorgeous.
Of course, all of this hardware design isn't possible without an open toolchain. There is an SRAM generator known as OpenRAM that can generate RAM blocks for your design. Coriolis2 is an RTL to GDS tool that can do placement and routing in VLSI. Finally, FlexCell is a cell library that tries to provide standard functions in a flexible, customizable way that cuts down on the complexity of the layout. There are GitHub actions that can run tests and simulations on PRs to keep the chip's HDL in a good state.
However, it's not all roses, and there was an error on the first run (MPW1). Hold time violations were not detected, and the clock tree wasn't correct. This means that the GPIO cannot be set up, so the designs in the middle could be working, but without the GPIO, it is tricky to determine. With a regular chip, that would be the end, but since [Matt] has access to both the layout and the design, he can identify the problem and come up with a plan. He's planning on overriding the IO setup shift register with an auxiliary microcontroller. (Ed Note: [tnt] has been making some serious progress lately, summarized in this video.)
It is incredible to see what has come from the project so far, and we're looking forward to future runs. If this convinces you that you need to get your own ASIC made, you should check out [Matt]'s "Zero to ASIC" course.
#cons #hackadaycolumns #hardware #2021hackadayremoticon #asic #fab
"Thus, our university has created a complete #VLSI chain as free software. It is called Coriolis and allows the design of an #ASIC from its #VHDL description to the drawing of the masks (see https://coriolis.lip6.fr)" https://lists.gnu.org/archive/html/libreplanet-discuss/2022-01/msg00141.html
