It's pretty cool to see how far RISC-V is coming along. It still has a way to go still but great progress to the RISC-V companies. #riscv #computers youtu.be/LX9Pz1TmEww?si=hAM33V…
#riscv
"An empirical comparison of the RISC-V and AArch64 instruction sets."
Just glancing through the paper (which is open access), it looks like RISC-V is competitive with ARM. They do 5 benchmarks, and for each one, it looks like they do a pretty sophisticated analysis, looking at path length, cycles per instruction, and length of the critical path. For most metrics, the ARM and RISC-V results are very close. When they're different the ARM processor usually does slightly better but there are actually some metrics where RISC-V does better.
"Our results show that the RISC-V ISA is not disadvantaged compared to the Arm AArch64 ISA in terms of potential performance for codes produced by today's compilers for HPC style workloads."
"With instruction counts largely within 10% of each other, and equivalent parallelism available, in most cases this leads to estimated equivalent run times for these architectures. Deeper analysis of STREAM shows that, with Arm's more powerful load and store instructions, path lengths have the potential to be much shorter than those presented. But with so many options available, the optimal solution is harder for compilers to find. In addition, with the inclusion of comparison instructions, AArch64 binaries require additional instructions when conditionally branching compared to RISC-V, potentially leading to up to 15% longer paths with all other instructions equivalent."
An empirical comparison of the RISC-V and AArch64 instruction sets
"BeagleBoard makes FPGA and RISC-V accessible with new BeagleV-Fire single board computer at $150."
BeagleBoard is offering a Raspberry-Pi alternative that uses a RISC-V processor. 5 cores (64-bit, 4 cores that can do floating point math + 1 core that is a special boot core), 3.125 Mhz (CoreMarks benchmark), 16 GB of memory, USB-C and Gigabit Ethernet.
The FPGA (field programmable gate array) has 23K logic elements (4-input LUT + DFF), 68 Math blocks (18x18 MACC), and 4 SerDes lanes. "Logic elements" are programmable logic gates: AND, OR, NOT, NAND, NOR, and XOR. "Math blocks" are blocks that perform arithmetic so you don't have to make arithmetic logic yourself out of logic gates. SerDes means "serializer/deserializer" and are how the FPGA communicates with the outside world.
The "LUT" and "DFF" part refers to "look-up-table" and "D flip-flop". LUT enables you to program gates using lookup tables, and D flip-flops give your logic element a little bit of digital memory. "18x18 MACC" means a multiply-accumulate block that can handle 18-bit numbers.
