So you have seen news about the recent earthquake. You also know Taiwan is producing around 90% of the world's leading edge semiconductors, and thus is bound to be affected by this in a special way.
Asianometry's Jon has this all detailed in this TSMC-focused video, which I recommend you watch.
So consultant Ian Cutress, who has a side business on youtube, gets to interview Pat Gelsinger, of 486 fame and effing Intel CEO. After he gave a keynote (Gelsinger, not Cutress, that is).
The strategic views are good and rich, but as those centre closely around the technologies in use today, the ex chip designer feels authentic to me. Specifically in moments around, say, 7:32 when its about Foveros Direct, and 9:01 when advanced packaging is on topic, "nice and simple". Or just when he says, understatement galore, that he is "judge and jury" on this decision of this or that, and how to lower customer's risks at 12:14.
While listening, keeping his features in check, he looks as stressed as any other CEO. Fully professional. But I sense the authenticity of an engineer, which I dig. Just sayin'.
"Intel unveiled a new roadmap that includes a new 14A node, the industry's first to use High-NA EUV, here at its Intel Foundry Services Direct Connect 2024 event."
Intel no longer uses "nanometers" to refer to its "process nodes", so I don't know what "14A" means, but, there is a quote somewhere of Intel CEO Pat Gelsinger saying 14A produces "1.4 nanometer technology." Maybe "14A" means 14 angstroms.
The other term in there is "High-NA EUV". "NA" stands for "numerical aperture". But to understand the significance of that we have to take a few steps back.
The company that makes the semiconductor manufacturing equipment is ASML (Advanced Semiconductor Materials Lithography).
Chips are made through a process called photolithography, which involves shining light through a chip design in such a way that it is miniaturized, and through a process using a lot of complicated chemistry, that pattern can be etched into the surface of the silicon and turned into an electronic circuit. These circuits have gotten so small that visible light has wavelengths too big to make the chip. Chipmakers predictably went to ultraviolet light, which has shorter wavelengths. That worked for a time, but suddenly a problem came up, which is that air was opaque to the wavelengths they wanted to use.
To us, we think of air as transparent, and for the visible wavelengths that our eyes use, it is pretty much perfectly transparent. But it is not transparent at all wavelengths. At certain ultraviolet wavelengths, it's opaque like black smoke.
This is why the semiconductor industry had to make the sudden jump from using lasers that emit light at 193 nanometers to lasers that emit light at 13.5 nanometers. (13.5 was chosen because people just happened to know how to make light at that frequency with a tin plasma laser.) Jumping the chasm from 193 to 13.5 jumps across the wavelengths where air is opaque. 193 has been called "deep ultraviolet", or DUV. 13.5 is called "extreme ultraviolet", or EUV. So whenever you see "EUV", which we see here in the phrase "Nigh-NA EUV", that's what it's talking about.
Making this jump required rethinking all the optics involved in making chips. Mainly this involved replacing all the lenses with mirrors. Turns out at 13.5 nanometers, it's easier to do optics with reflective mirrors than transparent lenses.
Besides decreasing the wavelength (and increasing the frequency) of the light, what else can be done?
It turns out there's two primary things that determine the limit of the size you cat etch: the light wavelength and the numerical aperture. There's some additional factors that have to do with the chemistry you're using for the photoresists and so fourth, but we'll not concern ourselves with those factors at the moment.
So what is numerical aperture? If you're a photographer, you probably already know, but it has to do with the angle at which a lens can collect light.
"The numerical aperture of an optical system such as an objective lens is defined by:
NA = n sin(theta)
where n is the index of refraction of the medium in which the lens is working (1.00 for air, 1.33 for pure water, and typically 1.52 for immersion oil), and theta is the half-angle of the maximum cone of light that can enter or exit the lens."
As for "the medium in which the lens is working", note that ASML used water immersion with deep ultraviolet (193 nanometer light and higher) to achieve an NA greater than 1. This hasn't been done for extreme ultraviolet (13.5 nanometer light).
The increase in numerical aperture that ASML has recently accomplished, and that Intel is announcing they are using, is an increase from 0.33 to 0.55. (Numerical aperture is a dimensionless number.)
How did ASML achieve this increase? Their page on "5 things you should know about High NA EUV lithography" (link below) gives a clue. One of the 5 things is, "larger, anamorphic optics for sharper imaging".
The page refers to "EXE" and "NXE". These refer to ASML's own equipment. NXE systems have a numerical aperture of 0.33, but with the EXE systems, ASML has increased it to 0.55.
"Implementing this increase in NA meant using bigger mirrors. But the bigger mirrors increase the angle at which light hit the reticle, which has the pattern to be printed."
You're probably not familiar with the term "reticle". Here the meaning is different from normal optics. In normal optics, it refers to a scale that you might see in a microscope scope. But here, it has to do with the fact that chips are no longer manufactured with the entire pattern for the whole chip all in one shot. Instead, a pattern for only a small portion of the wafer is used at a time, and then stepper motors move the wafer and the process is repeated. This small portion of the pattern that is used at a time is called the "reticle".
"At the larger angle the reticle loses its reflectivity, so the pattern can't be transferred to the wafer. This issue could have been addressed by shrinking the pattern by 8x rather than the 4x used in NXE systems, but that would have required chipmakers to switch to larger reticles."
"Instead, the EXE uses an ingenious design: anamorphic optics. Rather than uniformly shrinking the pattern being printed, the system's mirrors demagnify it by 4x in one direction and 8x in the other. That solution reduced the angle at which the light hit the reticle and avoided the reflection issue. Importantly, it also minimized the new technology's impact on the semiconductor ecosystem by allowing chipmakers to continue using traditionally sized reticles."
Mal ein Interview mit einer interessanten Expertin zum Thema Industriepolitik und Subventionen in der FAZ. Mariana Mazzzcato kannte ich zuvor nicht, aber ich streife das Feld ja auch nur.
Meine Lesart trifft das: was sie sagt Recht gut.
Europa braucht mehr Unabhängigkeit bei Halbleitern, und das Dutzend Milliarden ist gut investiert, vor allem dann wenn es denn gut investiert ist und auch in die Breite geht. Lies: Ausbildung und akademische Strukturen müssen mitgenommen werden. Hilft ja nix wenn Intel und die anderen alle kommen, aber deutschlandweit keine Köpfe nachwachsen. Wird das Unterfangen kein Generationennprojekt ist IPCEI II nur eine Luftnummer.
Link: https://m.faz.net/aktuell/wirtschaft/mehr-wirtschaft/mariana-mazzucato-habecks-lieblingsoekonomin-ueber-ihr-verhaeltnis-zum-minister-19509042.html (verschwindet bestimmt bald hinter Paywall)
Progressiv verstanden sollen Subventionen, so sie eigentlich als eine Anschubfinanzierung funktionieren, einen Rückfluss von Geld ermöglichen. Klingt besser als ein Tropf, aus dem ja eher keine Innovation zu erwarten ist. Ökosystem statt Gießkanne und Stickerwasser.
Mazzucato: Ich würde auch fordern: Wenn die Firma einen Gewinn macht, geht ein Teil davon zurück in den Innovationsfonds der Regierung. Auf solche Details kommt es an, wenn Sie ein schlauer unternehmerischer Staat sein wollen.FAZ: Was halten Sie von zehn Milliarden Euro für eine neue Intel-Fabrik in Magdeburg?
Das kann ich akzeptieren. Chip-Souveränität ist wichtig für Amerika und Europa, sonst kommen alle Chips aus Taiwan. Dies ist eine Chance, sicherzustellen, dass die Chipindustrie zu nachhaltigem Wachstum für alle beiträgt. Die USA machen ihr öffentliches Geld davon abhängig, dass die Unternehmen Arbeitsbedingungen verbessern, grüne Lieferketten verwenden und nicht nur Aktien zurückkaufen. Aber wie stellen Sie sicher, dass Sie über alle Aspekte nachdenken, über das ganze System? Dass man mit einer Subvention nicht ein neues Problem anderswo schafft?
Die Nachbarfirmen der neuen Intel-Fabrik in Magdeburg haben Angst, dass sie bald keine Mitarbeiter mehr finden.
Sie müssen systemisch denken, ein Ökosystem schaffen und nicht nur eine Firma subventionieren. Mit anderen Worten: Sie brauchen eine schlaue Industriepolitik, getrieben von einer Mission, die es zum Beispiel auch Start-ups ermöglicht, zu wachsen, statt nur einem großen Unternehmen eine Subvention zu zahlen.
#semiconductors #Europe #policy #Intel #Magdeburg #IPCEI #ipcei-ii
"Chinese-developed nuclear battery has a 50-year lifespan -- Betavolt BV100 built with Nickel-63 isotope and diamond semiconductor material."
"This 15 x 15 x 5mm battery delivers 100 microwatts at 3 volts. The company says multiple BV100 batteries can be used together in series or parallel depending on device requirements."
"The new BV100 is claimed to be a disruptive product on two counts. Firstly, a safe miniature atomic battery with 50 years of maintenance-free stamina is a breakthrough. Secondly, Betavolt claims it is the only company in the world with the technology to dope large-size diamond semiconductor materials, as used by the BV100."
Wow, I didn't even know diamond semiconductors were a thing.
"Betavolt says its atomic battery is very different from similarly described power cells developed by the US and USSR in the 1960s. It says that the old nuclear batteries were large, dangerous, hot, and expensive products. For example, some old-tech atomic batteries used Plutonium as the radioactive power source. Meanwhile, the Betavolt BV100 is claimed to be safe for consumers and won't leak radiation even if subjected to gunshots or puncture."
Graphene as a semiconductor? I thought it was impossible to turn graphene into a semiconductor because it doesn't have a big enough band gap. But researchers have developed a technique for combining graphene with silicon carbide. The graphene has better heat dissipation at higher density than silicon.
I'll have a closer look at this at some unspecified time in the future, but for now I'll give you all this quick overview from Sabine Hossenfelder.
This new semiconductor could revolutionize computing - Sabine Hossenfelder
"Teardown finds Huawei's 5nm notebook processor was made in Taiwan, not China."
"According to a teardown of Huawei's Qingyun L540 notebook by testers at TechInsights, the mysterious 5nm Kirin 9006C processor it contained was actually manufactured by Taiwan Semiconductor Manufacturing Co, not from a Middle Kingdom manufacturer."
"When the 14-inch ultralight first appeared in early December, the presence of a 5nm processor spurred furious speculation that China's domestic semiconductor manufacturing capability was far more advanced than previously thought."
Looks like the Chinese are not as advanced as I thought they might be.
Anyone here a Chinese chip expert, and want to explain the difference between Huawei's Kirin 9000S and 9006C?
Teardown finds Huawei's 5nm notebook processor was made in Taiwan, not China
For the first time, Chinese automaker BYD has overtaken Tesla, as the world's best-selling producer of electric vehicles.It delivered more than its US-based ...#BYD #Chineseelectricvehicles #EVbatteryshortage #EVtechnology #Electricvehicles #Tesla #automotiveindustry #china #chipmaking #electriccars #evbatteryindustry #microchips #powerchips #powerchipindustry #semiconductors #techwars #unitedstates #uschinatradewar #ussanctionsonchina #AlJazeera #AlJazeeraEnglish #alJazeera #aljazeeraEnglish #aljazeeralive #aljazeeravideo #aljazeeraEnglish #aljazeeralatest #aljazeeralive #aljazeeralivenews
China’s BYD surpasses Tesla as leading electric car seller
Japan and the Netherlands agreed "to tighten restrictions on the export of chip manufacturing technology to Chinese companies."
"ASML is the most critical company affected by the Netherlands' restrictions. It's the only company in the world that produces so-called ultraviolet lithography machines, which are critical to the production of advanced semiconductors. CNBC previously reported that the company was already unable to ship its advanced extreme ultraviolet lithography (EUV) machine to China but that it could still ship older deep ultraviolet lithography (DUV) machines."
"On the Japanese side, the restrictions are expected to impact companies such as Nikon and Tokyo Electron."
Japan and the Netherlands join US with tough chip controls on China
#solidstatelife #semiconductors #euv #asml #exportrestrictions #geopolitics
3 nanometer chips have arrived. "Today," (which was actually December 29), "TSMC announced that 3nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3nm technology will create end products with a market value of US$1.5 trillion within five years of volume production."
"Phases 1 through 8 of TSMC Fab 18 each have cleanroom area of 58,000 square meters, approximately double the size of a standard logic fab. TSMC's total investment in Fab 18 will exceed NT$1.86 trillion," -- NT is New Taiwan dollar -- this is $61 billion in US dollars -- "creating more than 23,500 construction jobs and over 11,300 high-tech direct job opportunities. In addition to expanding 3nm capacity in Taiwan, TSMC is also building 3nm capacity at its Arizona site."
"TSMC also announced that the Company's global R&D Center in the Hsinchu Science Park will officially open in the second quarter of 2023, to be staffed by 8,000 R&D personnel. TSMC is also making preparations for its 2nm fabs, which will be located in the Hsinchu and Central Taiwan Science Parks, with a total of six phases proceeding as planned."
"TSMC's 3nm process is the most advanced semiconductor technology in both power, performance, and area (PPA) and in transistor technology, and a full-node advance from the 5nm generation. Compared with the 5nm (N5) process, TSMC's 3nm process offers up to 1.6X logic density gain and 30-35% power reduction at the same speed, and supports the innovative TSMC FINFLEX architecture."
"China's SMIC shipping 7nm chips, reportedly copied TSMC's tech." Article from July but I just saw it today. If true, mainland China has much more advanced semiconductor manufacturing capability than I thought.
"According to analyst firm TechInsights, Chinese foundry SMIC has been producing chips based on its 7nm process node for a Bitcoin Miner SoC, and they've been shipping since July of 2021 (h/t to SemiAnalysis). TechInsights has reverse-engineered the chip, saying the 'initial images suggest it is a close copy of TSMC 7nm process technology,' a telling discovery after Taiwan-based TSMC has sued SMIC twice in the past for copying its tech."
"SMIC has been heavily sanctioned by the US government, restricting its access to advanced EUV chipmaking tools."
China's SMIC shipping 7nm chips, reportedly copied TSMC's tech
#Taiwan #China #semiconductors
Some considerable time ago, when the interwebs were all a-buzz about Pelosi's visit to Taiwan and I mentioned that TSMC was the main good reason for any American leader to go there, the push-back at the time was that chips weren't as important as all that. Up comes "60 Minutes" only TODAY to talk about life in Taiwan in which was mentioned the "silicon shield" aka the "chip shield". It's been a long time coming but now comes the time when I can say I TOLD YOU SO.
Commencing to be insufferably smug for the rest of the day.
https://www.cbsnews.com/video/taiwan-china-lesley-stahl-60-minutes-video-202210-02/
"Seven years ago, when the Epyc comeback plan was formulated, AMD could not have dreamed in a million years that Intel's vaunted foundries would run into so many troubles with 10 nanometer and then 7 nanometer processes. The current situation has created as big of a gap for AMD to exploit as Intel's stubborn decision to put forth the Itanium architecture as the future of datacenter compute back in the late 1990s and early 2000s."
"In the quarter ended in June, revenues for AMD were up 70.1 percent to $6.55 billion. Due to higher costs for development of products like the 'Genoa' and 'Bergamo' Epyc 7004, the 'Genoa-X' and Turin tweaks to the Epyc 7004 designs with Zen 4 cores, the 'Turin' and 'Siena' CPUs with Zen 5 cores coming further down the road in 2024, as well as the still-un-codenamed Instinct MI300A hybrid CPU-GPU compute engine coming next year, net income took a pretty big hit."
"Seven years ago, when the Epyc comeback plan was formulated, AMD could not have dreamed in a million years that Intel's vaunted foundries would run into so many troubles with 10 nanometer and then 7 nanometer processes. The current situation has created as big of a gap for AMD to exploit as Intel's stubborn decision to put forth the Itanium architecture as the future of datacenter compute back in the late 1990s and early 2000s."
"In the quarter ended in June, revenues for AMD were up 70.1 percent to $6.55 billion. Due to higher costs for development of products like the 'Genoa' and 'Bergamo' Epyc 7004, the 'Genoa-X' and Turin tweaks to the Epyc 7004 designs with Zen 4 cores, the 'Turin' and 'Siena' CPUs with Zen 5 cores coming further down the road in 2024, as well as the still-un-codenamed Instinct MI300A hybrid CPU-GPU compute engine coming next year, net income took a pretty big hit."
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