0 Persons are tagged with #risc-v

#risc-v

anonymiss@despora.de
anonymiss

#OrangePi Now has an #OpenSource #RISC-V SBC [With M.2 Slot]

source: https://news.itsfoss.com/orange-pi-rv/

TL;DR: The #CPU is too weak for a #desktop system. Without #HDMI, there are much cheaper IoT RISC-V systems.

The RISC-V chip it uses is the same one as found on the #Milk-V Mars, with Orange Pi pointing out that it can run Linux distributions, pointing to #Debian #Linux on its download page.

With Milk-V Mars, starting #Firefox takes 20 seconds under Debian. Nobody really wants to work with this #performance. You could certainly shorten the time with a very lightweight customized Linux, but it is questionable whether these adjustments will be made.

What's better is that #PCIe is on the underside, unlike the Mars, and the #Wifi is onboard.

enter image description here

If you are looking for a pure IoT solution without HDMI, the Milk-V Duo S is a much cheaper hardware that runs under Linux.

#news #microcontroller #gpio #usb

Orange Pi Now has an Open Source RISC-V SBC [With M.2 Slot]

A pretty interesting RISC-V powered SBC for tinkerers and developers.

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anonymiss@despora.de
anonymiss

Faulty instructions in #Alibaba's T-Head #C910 #RISC-V CPUs blow away all #security

source: https://www.theregister.com/2024/08/07/riscv_business_thead_c910_vulnerable/

When you use these flawed instructions, you will be touching physical #memory directly, bypassing the #MMU and its memory protection mechanisms that ordinarily prevent apps from interfering with each other and the underlying #OS and #hardware.

#cpu #fail #news #problem #exploit #ram

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anonymiss@despora.de
anonymiss

#Olimex Teases a Low-Cost Dual-Core #RISC-V Dev Board Built Around the Espressif #ESP32 - P4

source: https://www.hackster.io/news/olimex-teases-a-low-cost-dual-core-risc-v-dev-board-built-around-the-espressif-esp32-p4-84333cbefeaf

#Espressif's ESP32-P4 itself, meanwhile, comes with two RISC-V #microcontroller cores running at up to 400MHz and 768kB of static #RAM. Its general-purpose input/output (GPIO) connectivity, brought out to 0.1" pins on the development board's edges, include #SPI, #I2C, #I2S, #UART, #TWAI, and #SDIO Host 3.0 buses, pulse-width modulation (PWM), and analog to digital converter (ADC) support.

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#hardware #news #gpio #iot

Olimex Teases a Low-Cost Dual-Core RISC-V Dev Board Built Around the Espressif ESP32-P4

Two RISC-V cores running at up to 400MHz, 16MB of SPI flash, and a camera interface with 1080p H.264 encoder — plus on-board Ethernet.

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anonymiss@despora.de
anonymiss

Framework #Laptop 13 To See A #RISC-V #Motherboard Option

source: https://www.phoronix.com/news/Framework-Laptop-RISC-V-Board

"This Mainboard is extremely compelling, but we want to be clear that in this generation, it is focused primarily on enabling developers, tinkerers, and hobbyists to start testing and creating on RISC-V. The peripheral set and performance aren’t yet competitive with our Intel and AMD-powered Framework Laptop Mainboards. This board also has soldered memory and uses #MicroSD cards and #eMMC for storage, both of which are limitations of the processor. It is a great way to start playing with RISC-V though inside of a thin, light, refined laptop. The Mainboard will be able to drop into any Framework Laptop 13 chassis or into the Cooler Master Mainboard Case. DeepComputing is also working closely with the teams at Canonical and #RedHat to ensure Linux support is solid through #Ubuntu and #Fedora."

#cpu #hardware #news #linux #foss #floss

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scriptkiddie@anonsys.net
Script Kiddie

#Milk-V Duo S mini #PC with #RISC-V and #ARM processor cores

The versatility of the Milk-V Duo S is one of its standout features. It comes equipped with a range of connectivity options, including a 10/100 #Ethernet jack for stable wired internet connections and #USB Type-C and Type-A ports for connecting a variety of peripherals. The board also includes a #microSD card reader for expandable storage, and it’s equipped with 512MB of #DDR3 memory, which is more than capable of managing multiple tasks simultaneously. For those who need wireless connectivity, certain models of the Milk-V Duo S also include #WiFi and #Bluetooth, as well as #eMMC storage options for faster data access and improved security.

...

With a starting price of only $11, it is positioned to be within reach of a wide spectrum of users, from hobbyists to professionals.

see: geeky-gadgets.com/mini-pc-with…

Runs with #Linux: milkv.io/docs/pioneer/getting-…

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#linux #hardware #microcomputer #news #cpu #npu #iot

Pfsense Box mini PC with 6 Gigabit Ethernet from $417

A new mini PC equipped with 6 Gigabit Ethernet ports has been recently launched powered by an Intel Core i5-1135G7 processor

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california@diaspora.permutationsofchaos.com
California Girls Hacker

Tinker board in #RaspberryPi format has #RISC-V #CPU

URI: https://www.beagleboard.org/boards/beaglev-fire

  • 4x 64-bit #RV64GC Application cores (U54-MC)
  • Fmax of 667 MHz (–40 °C to 100 °C Tj)
  • 2GB LPDDR4
  • 16GB Kingston #eMMC
  • 128Mbit SPI flash
  • #USB Type-C with high-Speed (480Mbps) dual-role support and power input
  • Gigabit #Ethernet
  • M.2 E-Key socket for #WiFi and other #PCIe/SDIO modules
  • microSD card socket
  • Price $150

BeagleVFire

#hardware #iot #technology #beagleboard #BeagleVFire

BeagleV®-Fire

New BeagleV-Fire features FPGA and RISC-V CPU and is available now around $150. Credit-card sized, Linux-enabled board based on Microchip Polarfire SoC offers high-speed I/O with BeagleBone cape compatible headers and SYZYGY and M.2 connectors.

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anonymiss@despora.de
anonymiss

#RISC-V #technology emerges as battleground in US-China tech #war

source: https://www.reuters.com/technology/us-china-tech-war-risc-v-chip-technology-emerges-new-battleground-2023-10-06/

Jack Kang, vice president of #business #development at #SiFive, a Santa Clara, #California - based startup using RISC-V, said potential U.S. #government #restrictions on American companies regarding RISC-V would be a "tremendous tragedy."

"It would be like banning us from working on the internet," Kang said. "It would be a huge mistake in terms of technology, leadership, innovation and companies and jobs that are being created."

#China #USA #fail #trade #chip #cpu #news #regulation #restriction #future #openHardware #Hardware #politics #problem #America #economy

US-China tech war: RISC-V chip technology emerges as new battleground

In a new front in the U.S.-China tech war, President Joe Biden's administration is facing pressure from some lawmakers to restrict American companies from working on a freely available chip technology widely used in China - a move that could upend...

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anonymiss@despora.de
anonymiss

The open chip #Caliptra will hopefully replace #proprietary developments like #Microsoft #Pluton.

source: https://www.opencompute.org/blog/cloud-security-integrating-trust-into-every-chip

The #OCP Foundation is pleased to provide a collaborative #framework where #AMD, #Google, Microsoft, and #NVIDIA came together to define a scalable and standards-based #solution for the benefit of the entire #industry.

#trust #cloud #server #technology #risc-v #open #freedom #hardware #news #security

Open Compute Project

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anonymiss@despora.de
anonymiss

#RISC-V based #GPU Processor

source: https://www.think-silicon.com/neox-graphics

NEOX™ is a parallel multicore and multithreaded GPU #architecture based on the RISC-V RV64C ISA instruction set with adaptive NoC. The number of cores varies from 4 to 64 organized in 1-16 cluster elements, each configured for cache sizes and thread counts . Depending on cluster / core configuration, NEOX™ compute power is ranging from 12.8 to 409.6 GFLOPS at 800MHz with support for FP16, FP32 and optionally FP64 and SIMD instructions.

Does anyone know how far #LibreRISC is with their GPU?

#news #hardware #graphic #neox #riscv

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hackbyte@friendica.utzer.de
hackbyte (friendica) 13HB1

Wy don't we have already mainframe class operating systems, interconnects and high level language abstractions on top of Open RISC-V ISA designs?

What is a fricking #MainFrame system? It's a very specific ISA, implemented in a so many Virtual Machine Layers .. heck they even call themselves #LPARs (Logical Partitions). That it is nowadays run on a _bunch_ of different processors... All just coded down to give the optimum peak performance for decades old layers of code, whlie guaranteeing every single transaction.

Heck we develop RISC-V for rad hardnened stuff already, creating a quorum of several cores to make sure there is no error...

When will we enter the real space of big calculations and big transactions finally? ;)

#RISC-V #MainFrame #Hardened #Quorum

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