We discovered the Red #Unlock technique that allows extracting #Intel Atom #Microcode
source: https://github.com/chip-red-pill/MicrocodeDecryptor
List of Supported CPUs: https://github.com/chip-red-pill/MicrocodeDecryptor#list-of-supported-cpus=
#cpu
#Hertzbleed is a new family of side-channel attacks: #frequency side channels.
Source: https://www.hertzbleed.com
Hertzbleed takes advantage of our experiments showing that, under certain circumstances, the dynamic frequency scaling of modern x86 processors depends on the data being processed. This means that, on modern processors, the same program can run at a different CPU frequency (and therefore take a different wall time) when computing, for example, 2022 + 23823 compared to 2022 + 24436.
...
Am I affected by Hertzbleed? Likely, yes.
#cpu #x86 #security #Encryption #news #attack #hack #vulnerability #problem #software #hardware
#Linux 5.18 officially released, #Intel #processor #SDSi in-app purchase feature online
Some users worry that Intel is exploring a new business model by launching SDSi. Under this “business model”, Intel #CPU features will be disabled by default until the user “pays” an additional fee to obtain a corresponding license to “unlock” full functionality.
Bullshit Intel has a #KillSwitch for its CPUs and the power to turn off all CPUs. I don't want that kind of #crap in my CPU. Please do not support this by promoting this #business model. Do not buy Intel CPUs anymore!
#Technology #fail #wtf #omg #feature #hardware #problem #news #economy #bullshit
#Debian: #Firmware - what are we going to do about it?
source: https://blog.einval.com/2022/04/19
TL;DR: firmware support in Debian sucks, and we need to change this. See the "My preference, and rationale" Section below.
...
For Debian's purposes, we typically separate firmware from software by considering where the code executes (does it run on a separate processor? Is it visible to the host OS?) but it can be difficult to define a single reliable dividing line here. Consider the Intel/AMD #CPU #microcode packages, or the U-Boot firmware packages as examples.
#Intel has patented the #Zen #microarchitecture from #AMD
source: https://nitter.eu/underfox3/status/1511697355145367564
@Dr. Roy Schestowitz (罗伊) #fail #patent #economy #competitor #wtf #omg #cpu #technology #invention #news #capitalism #politics #justice
Is #Bitcoin broken by #design?
#Bitcoins are supposed to be a #decentralized alternative global #currency. Originally, everyone was supposed to participate in #mining with their #CPU and thereby achieve decentralization. If this were the case, cryptocurrency could be operated today via Raspberry Pies in a power-saving manner, because the complexity of the mining adapts to the CPU #power that is available. But #greed tempted some participants to use server farms to earn more via mining. Of course, this increased the pressure on others to follow, since they also wanted to get a piece of the pie. Consequently, more and more #hardware and energy was wasted on mining.
#capitalism #environment #energy #waste #crypto #blockchain #problem #fail #gpu #technology #future
Zumindest das #Wissen wie man eine #CPU baut ist in #Deutschland noch vorhanden sogar auf Weltrekordniveau, jetzt bräuchte es nur noch entsprechende Fertigung in #Europa.
Siehe: https://www.nordstadtblogger.de/fh-dortmund-entwickelt-neuartigen-it-baustein/
„Erste Tests mit dem Chip bestätigen, dass er korrekt funktioniert“, berichtet Alexander #Walsemann, der die Ergebnisse bereits weiteren Forschenden in einem Workshop in Hannover vorgestellt hat. Als nächstes stehen umfangreiche Überprüfungen an, dazu gehören Studien mit Röntgenstrahlen und Schwer-Ionen. „Aufgrund der angewendeten Techniken erwarten wir eine äußerst hohe #Strahlentoleranz von bis zu 100 #Megarad – das wäre ein weltweiter Rekord“, betont Betreuer Michael #Karagounis.
#Strahlung #Weltraum #RISC-V #Hardware #Dortmund #Wissenschaft #Rekord #Forschung
A #RaspberryPi with #RISC-V is quite unlikely in the near future
source: https://www.theregister.com/2022/02/28/pi_at_10/
As for the future, a Raspberry Pi 5 is inevitable but, in a blow to those hoping for something even more exotic in the usually #Broadcom Arm #SoC, RISC-V isn't on the cards, certainly not in the timeframe for the next generation of Pi. "I can't go out today and license a RISC-V core," says Upton, citing the current state of the ecosystem, "which is even as good as the core of the Raspberry Pi 4."
...
The implosion of the #Nvidia / #Arm deal has also reduced the chances of a RISC-V Pi (in the 2030 timeframe), down from 20 per cent to 10 per cent, according to #Upton.
#hardware #news #opensource #freedom #economy #interview #cpu #gpu
Doomed from the start? Why #Nvidia failed to buy #Arm from #SoftBank
source: https://www.cnbc.com/2022/02/08/nvidia-arm-deal-may-have-been-doomed-from-the-start.html
Before long, competition regulators in the U.S., the U.K., #China and #Europe were investigating the #deal from all angles, leading tech investors and analysts to speculate that the acquisition would never gain #approval.
So I had wished that the deal would be successful, because that would have catapulted the free architecture #RISC-V to the front. China would then no longer have relied on proprietary ARM CPUs.
#Technology #CPU #digital #economy #problem #politics #news #freedom #USA #trade #future
fascinating video(s)
thanks for making & sharing 🙂 will do the best to assemble an informative article 🙂
https://ytpak.net/watch?v=CkNn98WE5_k
https://ytpak.net/watch?v=oIiqVrKDtLc
market share of players
fascinating book
“If (when!) it works it’s going to be glorious, but that’s not to underestimate the challenges of getting there!”
Ångstrom Era
when semiconducters are smaller than 1nm (nanometer)
1 Å = 0.1 nanometre = 100 picometres
“Although deprecated by both the International Bureau of Weights and Measures (BIPM) and the US National Institute of Standards and Technology (NIST), the unit is still often used in the natural sciences and technology to express sizes of atoms, molecules, microscopic biological structures, and lengths of chemical bonds, arrangement of atoms in crystals, wavelengths of electromagnetic radiation, and dimensions of integrated circuit parts” (src: Wiki)
why did intel not go with picometers then? 🤔 (ANGST!)
“Cautions In Using High-NA EUV”
Frederick Chen (Advanced Memory Development at Winbond Electronics)
Published Sep 20, 2021
“High-NA EUV has received a lot of attention ever since Intel put the spotlight on its receiving the first 0.55 NA EUV tool from ASML [1], expected in 2025. EUV itself has numerous issues which have been enumerated by myself and others, most notoriously the stochastic defects issue. There are also a host of issues related to the propagation of the EUV light in 3D through the mask topology, with shadowing being the easiest description of the phenomenon [2]. It has already been disclosed by one EDA vendor, in fact, that EUV is being practiced with multipatterning [3], defeating the purpose for which it was originally intended. So, with the entry of high-NA EUV, the prospect of single patterning EUV makes it a very attractive option. What changes can we aspect with a high-NA EUV system compared to the current EUV system?”
“Improvements with High NA”
“The high NA increases the numerical aperture (NA) from the current value of 0.33 to 0.55. The first benefit is this decreases the minimum optical spot size to 60% of its current value. The nominal value is given by the Rayleigh criterion of 0.61*nominal wavelength(=13.5 nm)/NA, which is 25 nm for 0.33 NA and 15 nm for 0.55 NA. This, of course, helps gives a sharper aerial image, i.e., the classically projected image at the focused point in space. In reality, the image is noisier due to the limited number of photons and blurred by electrons and chemical species in the resist.
A second benefit from the high-NA system is the increased demagnification in the Y-direction (from 4X to 8X). This has the effect of reducing the spread of angles. Keeping the original 4X would have resulted in a prohibitive range of angles. This helps reduce the impact of the 3D propagation through the mask mentioned earlier. Furthermore, since the X-demagnification is the same, there is also a reduction in the range of azimuthal rotation of the plane of incidence through the slit. The illumination sine ratio (kx/4)/(ky/8) = 2 kx/ky on the mask is halved to kx/ky on the wafer, whereas for the current imaging systems the same ratio (kx/4)/(ky/4) on the mask is preserved as kx/ky on the wafer. Thus, this improves the illumination consistency through the slit.
Complications/Tradeoffs with High NA
There are three issues with the move to a higher NA. The first should be well-known to lithographers, since it is the reduced depth of focus [4]. While the 0.33 NA 13.5 nm wavelength gives a depth of focus of 120 nm, increasing the NA to 0.55 reduces the depth of focus to a third of that, 41 nm.
The second issue is a consequence of the 8x Y-demagnification. Since the EUV mask 104 mm x 132 mm field size is not changing, the scanned field on the wafer has to be halved (in Y) from 26 mm x 33 mm to 26 mm x 16.5 mm. If a chip pattern originally took up over half the 26 mm x 33 mm field (as usually the case, even as 3 x 3 dies, for example), it would be chopped midway, leading to the need to stitch the two parts together through the exposure of two masks. Hence, double exposure patterning may creep in, spoiling the single patterning scenario.
The third issue is definitely a gotcha, since it was supposed to have been avoided at all costs in previous lithography system designs. The use of larger mirrors in the high-NA EUV system has led to unavoidable obscuration, where one mirror cannot avoiding blocking another. This has fundamental optical consequences, particularly reduction of modulation at lower spatial frequencies [5]. In some cases, the effects can be very drastic. In the example of a staggered 40 nm x 70 nm array below, one of the diffraction orders is obstructed by the central obscuration in the pupil of the 0.55 NA system.”
“In this example, it would lead to a doubling of the spatial frequency in the y-direction, which is a basic imaging error. The required modulation of the fundamental spatial frequency in the y-direction is eliminated when it should be kept for this pattern. Since much of the pupil is covered by forbidden illumination zones (shown in pink), this is difficult to integrate with other patterns which normally require more flexible illumination. For larger pitches of the same staggered array pattern, the zones would crowd closer together, allowing even less flexibility. This is something the high-NA EUV user has to be especially aware of.
No, stochastics will not go away
The use of higher NA reduces the spot size, and hence, the image pixel size is also effectively reduced. We also expect the resist blur to be reduced in order to take advantage of higher resolution. Hence, at the same dose and k1 (feature size normalized to wavelength/NA), the number of photons in the same number of edge pixels will continue to decrease. This means the stochastic issues of EUV imaging will persist at the feature edge.”
“References
[2] A. Erdmann et al., “3D mask effects in high NA EUV imaging,” Proc. SPIE 10957, 109570Z (2019).
[3] https://www.ednasia.com/multi-patterning-strategies-for-navigating-the-sub-5-nm-frontier-part-3/
[4] B. J. Lin, “The k3 coefficient in nonparaxial l/NA scaling equations for resolution, depth of focus, and immersion lithography” J. Micro/Nanolith. MEMS MOEMS 1(1) 7–12 (April 2002).
[5] S. T. Yang et al., “Effect of central obscuration on image formation in projection lithography,” Proc. SPIE 1264, 477 (1990).”
src: linkedin.com
Links:
https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography
#linux #gnu #gnulinux #opensource #administration #sysops #cpu #hardware #amd #intel #ai #superpower #china #taiwan #asml #tsmc #arm
Originally posted at: https://dwaves.de/2021/11/13/ai-superpowers-china-silicon-valley-and-the-new-world-order-kai-fu-lee-light-and-silicon-extreme-ultra-violet-cpu-production-asml-netherlands-tsmc-taiwan-amd-intel-usa-and-the-crazy-phys/
fascinating video(s)
thanks for making & sharing 🙂 will do the best to assemble an informative article 🙂
https://ytpak.net/watch?v=CkNn98WE5_k
https://ytpak.net/watch?v=oIiqVrKDtLc
market share of players
fascinating book
https://duckduckgo.com/?q=China+Silicon+Valley+And+The+New+World+&ia=web
“If (when!) it works it’s going to be glorious, but that’s not to underestimate the challenges of getting there!”
Ångstrom Era
when semiconducters are smaller than 1nm (nanometer)
1 Å = 0.1 nanometre = 100 picometres
“Although deprecated by both the International Bureau of Weights and Measures (BIPM) and the US National Institute of Standards and Technology (NIST), the unit is still often used in the natural sciences and technology to express sizes of atoms, molecules, microscopic biological structures, and lengths of chemical bonds, arrangement of atoms in crystals, wavelengths of electromagnetic radiation, and dimensions of integrated circuit parts” (src: Wiki)
why did intel not go with picometers then? 🤔 (ANGST!)
“Cautions In Using High-NA EUV”
Frederick Chen (Advanced Memory Development at Winbond Electronics)Published Sep 20, 2021
“High-NA EUV has received a lot of attention ever since Intel put the spotlight on its receiving the first 0.55 NA EUV tool from ASML [1], expected in 2025. EUV itself has numerous issues which have been enumerated by myself and others, most notoriously the stochastic defects issue. There are also a host of issues related to the propagation of the EUV light in 3D through the mask topology, with shadowing being the easiest description of the phenomenon [2]. It has already been disclosed by one EDA vendor, in fact, that EUV is being practiced with multipatterning [3], defeating the purpose for which it was originally intended. So, with the entry of high-NA EUV, the prospect of single patterning EUV makes it a very attractive option. What changes can we aspect with a high-NA EUV system compared to the current EUV system?”
“Improvements with High NA”
“The high NA increases the numerical aperture (NA) from the current value of 0.33 to 0.55. The first benefit is this decreases the minimum optical spot size to 60% of its current value. The nominal value is given by the Rayleigh criterion of 0.61*nominal wavelength(=13.5 nm)/NA, which is 25 nm for 0.33 NA and 15 nm for 0.55 NA. This, of course, helps gives a sharper aerial image, i.e., the classically projected image at the focused point in space. In reality, the image is noisier due to the limited number of photons and blurred by electrons and chemical species in the resist.
A second benefit from the high-NA system is the increased demagnification in the Y-direction (from 4X to 8X). This has the effect of reducing the spread of angles. Keeping the original 4X would have resulted in a prohibitive range of angles. This helps reduce the impact of the 3D propagation through the mask mentioned earlier. Furthermore, since the X-demagnification is the same, there is also a reduction in the range of azimuthal rotation of the plane of incidence through the slit. The illumination sine ratio (kx/4)/(ky/8) = 2 kx/ky on the mask is halved to kx/ky on the wafer, whereas for the current imaging systems the same ratio (kx/4)/(ky/4) on the mask is preserved as kx/ky on the wafer. Thus, this improves the illumination consistency through the slit.
Complications/Tradeoffs with High NA
There are three issues with the move to a higher NA. The first should be well-known to lithographers, since it is the reduced depth of focus [4]. While the 0.33 NA 13.5 nm wavelength gives a depth of focus of 120 nm, increasing the NA to 0.55 reduces the depth of focus to a third of that, 41 nm.
The second issue is a consequence of the 8x Y-demagnification. Since the EUV mask 104 mm x 132 mm field size is not changing, the scanned field on the wafer has to be halved (in Y) from 26 mm x 33 mm to 26 mm x 16.5 mm. If a chip pattern originally took up over half the 26 mm x 33 mm field (as usually the case, even as 3 x 3 dies, for example), it would be chopped midway, leading to the need to stitch the two parts together through the exposure of two masks. Hence, double exposure patterning may creep in, spoiling the single patterning scenario.
The third issue is definitely a gotcha, since it was supposed to have been avoided at all costs in previous lithography system designs. The use of larger mirrors in the high-NA EUV system has led to unavoidable obscuration, where one mirror cannot avoiding blocking another. This has fundamental optical consequences, particularly reduction of modulation at lower spatial frequencies [5]. In some cases, the effects can be very drastic. In the example of a staggered 40 nm x 70 nm array below, one of the diffraction orders is obstructed by the central obscuration in the pupil of the 0.55 NA system.”
“In this example, it would lead to a doubling of the spatial frequency in the y-direction, which is a basic imaging error. The required modulation of the fundamental spatial frequency in the y-direction is eliminated when it should be kept for this pattern. Since much of the pupil is covered by forbidden illumination zones (shown in pink), this is difficult to integrate with other patterns which normally require more flexible illumination. For larger pitches of the same staggered array pattern, the zones would crowd closer together, allowing even less flexibility. This is something the high-NA EUV user has to be especially aware of.
No, stochastics will not go away
The use of higher NA reduces the spot size, and hence, the image pixel size is also effectively reduced. We also expect the resist blur to be reduced in order to take advantage of higher resolution. Hence, at the same dose and k1 (feature size normalized to wavelength/NA), the number of photons in the same number of edge pixels will continue to decrease. This means the stochastic issues of EUV imaging will persist at the feature edge.”
“References
[2] A. Erdmann et al., “3D mask effects in high NA EUV imaging,” Proc. SPIE 10957, 109570Z (2019).
[3] https://www.ednasia.com/multi-patterning-strategies-for-navigating-the-sub-5-nm-frontier-part-3/
[4] B. J. Lin, “The k3 coefficient in nonparaxial l/NA scaling equations for resolution, depth of focus, and immersion lithography” J. Micro/Nanolith. MEMS MOEMS 1(1) 7–12 (April 2002).
[5] S. T. Yang et al., “Effect of central obscuration on image formation in projection lithography,” Proc. SPIE 1264, 477 (1990).”
src: linkedin.com
Links:
https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography
#linux #gnu #gnulinux #opensource #administration #sysops #cpu #hardware #amd #intel #ai #superpower #china #taiwan #asml #tsmc #arm
Originally posted at: https://dwaves.de/2021/11/13/ai-superpowers-china-silicon-valley-and-the-new-world-order-kai-fu-lee-light-and-silicon-extreme-ultra-violet-cpu-production-asml-netherlands-tsmc-taiwan-amd-intel-usa-and-the-crazy-phys/
#Intel processors Core i-12000: #Copy #protection crashes #games
source: https://news.in-24.com/news/257112.html
More than 50 games do not run properly if you start them on a desktop #PC with a processor from Intel’s Alder Lake-S series such as the Core i9-12900K. The copy protection mechanisms used by the publisher for digital rights management (DRM) are to blame – Intel cites #Denuvo’s software as the most prominent example.
#DRM makes games more expensive, costs electricity and computing power and reduces the gaming experience. It's a no-win #software because it punishes legitimate players.
#gamer #fail #wtf #performance #economy #news #cpu #patch #entertainment
